given how big GF's SRAM blocks are at the small end (64 words is half the size of 512!), do you think it'd end up being more area-efficient to just use registers/flip flops for small "sram-like" banks? say 16 words / 128 bits?
aha ok. so with some generous assumptions on the overhead plumbing, a 16x8 might looks something like this (albeit witih flexibility to smoosh into odd corners due to being not a macro block)
Have you seen: https://github.com/AUCOHL/DFFRAM
Their approach is to create a macro block containing standard cells for different memory configurations. This can be more dense than just having a large FF based RAM along with your RTL, and in theory speeds up synth/PnR. I'd suspect the final QoR ends up slightly worse.
@BreakingTaps : One reason the GF SRAMs don't scale well is that they all contain the same 10-bit address decoder and sense amps designed for a 128-row array.
generated a few latch and dff banks using dffram, neat project! latches were consistently 10-15% smaller than dff, and as expected they are all quite a bit bigger than the foundry optimized banks. Not really a fair comparison, will probably run some tests comparing it against a dumb register array since that's a lot closer to the use case
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